Integrated circuits typically operate based on a reference clock. The clock may be distributed to the various devices that utilize the clock. Clock distribution and balancing are generally important in certain integrated circuit designs. For example, clock distribution and balancing may be important in large, high performance, low power application specific integrated circuit (ASIC) designs. A clock tree may provide a representation of clock distribution and may be useful in balancing the clocks of the clock tree.
Clock skew generally includes a clock phase delay difference between two or more points in a clock tree. Clock skew may be desirable in certain integrated circuits. For example, clock skew may allow a circuit designer to borrow time from non-critical paths to meet timing of critical paths, by increasing the effective clock cycle time for example. As another example, clock skew may reduce voltage drop and electromagnetism caused by simultaneous clock switching. However, it is typically desirable to reduce or eliminate clock skew because clock skew may degrade design speed and cause malfunctions due to hold time violations. For example, thousands of hold time violations may result from a mere 100 ps increase in clock skew. Clock skew may also cause setup time violations on critical paths of the clock tree when the clock skew reduces the effective clock period. In ASIC designs, it may be desirable to control clock skew to be less than the register hold time constraints defined in a cell library. This may allow the registers to be connected to each other, such as in scan chains, without hold time violations.
Clock skew may be reduced or eliminated by balancing the clocks in a clock tree for a particular clock distribution. Current solutions for clock balancing generally require clocks to be balanced manually. For a device that includes approximately 600,000-700,000 flip-flops, for example, it could take several months to manually balance the clocks. Current clock tree synthesis (CTS) tools such as the APOLLO CTS may be used to automatically balance clocks; however, these CTS tools may lack a desired level of intelligence and may only be able to balance one path or one set of paths. Furthermore, the APOLLO CTS tool can only balance a single mode of operation. In general, CTS tools are unsatisfactory when the clock structure is complex, implements intensive clock-gating logic, or implements multiple modes of clock distribution.